1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to apparatus and methods of deflecting cracks in semiconductor chips.
2. Description of the Related Art
Conventional semiconductor chips are routinely fabricated en masse in large groups as part of a single semiconductor wafer. At the conclusion of the processing steps to form the individual dice, a so-called dicing or sawing operation is performed on the wafer to cut out the individual dice. Thereafter, the dice may be packaged or directly mounted to a printed circuit board of one form or another. Conventional semiconductor dice are routinely cut out from the wafer as rectangular shapes. Many conventional semiconductor dice have four sides and four corners. The dicing operation is a mechanical cutting operation performed with a type of circular saw. Dicing saws are made with great care and operate more precisely than a comparable masonry circular saw. Despite these refinements, the dicing saw still imposes significant stresses on the individual dice as they are cut. These stresses and impact loads during the cutting operation can cause microscopic fractures in the dice, particularly at the die edges and corners. Once the cut dice are mounted to a package substrate or printed circuit board of one sort or another, the cracks introduced during cutting may propagate further into the center of the dice due to thermal stresses and other mechanical stresses that may be placed on the die. In addition, new cracks may form, particularly near the corners which create so-called stress risers by virtue of their geometries.
A conventional technique for addressing the propagation of cracks from the corners of a die involves the use of a crack stop. A conventional crack stop consists of a frame-like structure formed in and near the edges of the semiconductor die. When viewed from above, the crack stop looks like a picture frame. The conventional crack stop has a vertical profile, much like a fortress wall. One conventional variant also incorporates a surface-located continuous trench.
Many current semiconductor chip designs include an interconnect stack consisting of plural metallization and interlevel dielectric layers. During or subsequent to the dicing operation, delaminations of the interlevel dielectric layers can occur and propagate toward the sensitive interior areas of the die. A delamination of sufficient severity can possibly proceed laterally inward, and if unimpeded by a conventional crack stop, lay waste to the delicate circuit structures in the die interior.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.